DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore

Doppelgänger: a cache for approximate computing

Modern processors contain large last level caches (LLCs) that consume substantial energy and area yet are imperative for high performance. Cache designs have improved dramatically by considering reference locality. Data values are also a source of optimization. Compression and deduplication exploit data values to use cache storage more efficiently resulting in smaller caches without sacrificing...

Moola: Multicore Cache Simulator

Chip multiprocessors have become the normative architecture for medium and high performance processors. These devices introduce new questions and research topics. One such topic is exploring the design space of a cachememory hierarchy that prevents the memory accesses from being a limiting factor on system performance. Simulation of system workloads is a widely accepted method for evaluating pr...

Resilience-Driven STT-RAM Cache Architecture for Approximate Computing

High-end manycore microprocessors exhibit large-sized caches (32MB – 128MB) that consume a significant amount of total energy. These caches are typically composed of 6T-SRAM cells, which lack efficiency in terms of area and leakage power [1][2]. The emerging memory technologies, like Spin-Transfer Torque RAM (STT-RAM), not only incur reduced leakage power but also provide high integration densi...

A Power Aware Cache and Register File Design Space Exploration

Cache-Conscious Query Processing

Foundations A cache is a hardware unit that speeds up access to data. Several cache units may be present at various levels of the memory hierarchy, depending on the processor architecture. For example, a processor may have a small but fast Level-1 (L1) cache for data, and another L1 cache for instructions. The same processor may have a larger but slower L2 cache storing both data and instructio...